The present invention relates generally to integrated circuits that perform data processing such as microprocessors, microcontrollers, logic circuitry, etc., and more particularly to reducing power consumption of such integrated circuits.
Modern day microprocessors, microcontrollers, logic circuitry, etc., (i.e., processing integrated circuits) consume a large portion of their power budget during AC operation (e.g., when circuitry is active and is processing instructions and/or data). While many power management techniques exist that attempt to reduce power consumption in sections of processing integrated circuits that are not in use (e.g., inactive sections of processing integrated circuits), maintaining a power budget for active sections of such circuitry remains difficult.
Most conventional techniques for budgeting power consumption of active sections of processing integrated circuits rely on reducing logic toggles through the use of multiplexers, or reducing logic toggles performed by control logic. For example, U.S. Pat. No. 6,054,877, which is hereby incorporated by reference herein in its entirety, discloses a xe2x80x9cTransition-Once MUXxe2x80x9d that may prevent multiplexer (MUX) output transitions for invalid data and reduce AC power consumption due to such xe2x80x9cinvalidxe2x80x9d MUX output transitions. Likewise, U.S. Pat. No. 6,237,101, which is hereby incorporated by reference herein in its entirety, discloses a technique for reducing power consumption of a microprocessor during decoding of a current instruction by maintaining control signals at the values/levels determined during the decoding of a preceding instruction if it is not necessary to change the values/levels of the control signals to execute the current instruction.
Another conventional technique for controlling power consumption in portable personal computers is disclosed in U.S. Pat. No. 6,167,524, which is hereby incorporated by reference herein in its entirety. U.S. Pat. No. 6,167,524 discloses, for example, summing expected power consumption values of active execution units to determine whether an expected total power consumption exceeds an optimum battery power efficiency value. If so, the amount of execution unit activity is rationed (e.g., so that power drain remains within a regime of optimum battery/converter efficiency). (Col. 6, lines 47-61). The expected power consumption value for each execution unit may be based on an average toggling power associated within the execution unit as computed via simulation. (Col. 5, line 60-col. 6, line 3).
These and other power management techniques do not take into account the actual data being operated on during a current clock cycle, and/or do not allow for real-time power balancing, particularly once an instruction is dispatched to an execution unit. Accordingly, maintaining a power budget for active sections of processing integrated circuits remains difficult.
In accordance with a first aspect of the invention, a method is provided for conserving power in a processing integrated circuit. The method includes the steps of (1) calculating power consumption for executing an instruction and data corresponding to the instruction; and (2) executing the instruction if such execution does not exceed a predetermined power level.
In accordance with a second aspect of the invention, a method is provided for conserving power in a processing integrated circuit employing a plurality of execution units. The method includes the steps of (1) comparing a total power to be consumed by the processing integrated circuit to a power budget for the processing integrated circuit; and (2) if the total power exceeds the power budget, freezing execution of an instruction by one of the plurality of execution units so as to allow execution of the instruction to continue at a later time from where execution was frozen. Numerous other aspects of the invention are provided, as are systems and apparatus.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.